MK2049-45 Datasheet Clock Pll

Manufacturer: Renesas

Overview: 3.3 VOLT COMMUNICATIONS CLOCK PLL DATASHEET MK2049-45.

Datasheet Details

The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation.

The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter.

The second PLL is a translator for frequency multiplication.

Packaged in 20 pin SOIC.
3.3 V + 5% operation.
Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E.
Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz.
Locks to 8 kHz + 100 ppm (External mode).
Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs.
Exact internal ratios enable zero.

Brand Logo	Part Number	Description	Manufacturer
	MK2049-45	3.3V Communications Clock PLL	Integrated Circuit Systems

Part Number	Description
MK2049-45	CLOCK PLL
MK2049-34	CLOCK VCXO PLL
MK2049-36	CLOCK PLL
MK2302-01	MULTIPLIER AND ZERO DELAY BUFFER
MK2304-2	LOW SKEW BUFFER
MK2308-2	LOW SKEW BUFFER
MK2703	PLL AUDIO CLOCK SYNTHESIZER
MK2703B	PLL AUDIO CLOCK SYNTHESIZER
MK2705	AUDIO CLOCK SOURCE
MK2712	NTSC/PAL Clock