MK2049-45 - CLOCK PLL

Product Overview

Renesas

Part number	MK2049-45
Manufacturer	Renesas
File Size	377.46 KB
Description	CLOCK PLL
Datasheet	MK2049-45 Datasheet
Additional preview pages of the MK2049-45 datasheet.

The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation.

The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter.

The second PLL is a translator for frequency multiplication.

Packaged in 20 pin SOIC.
3.3 V + 5% operation.
Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E.
Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz.
Locks to 8 kHz + 100 ppm (External mode).
Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs.
Exact internal ratios enable zero.

📁 Similar Datasheet

MK2049-45 - 3.3V Communications Clock PLL (Integrated Circuit Systems)
MK2049-01 - Communications Clock PLL (Integrated Circuit Systems)
MK2049-02 - Communications Clock PLLs (Integrated Circuit Systems)
MK2049-03 - Communications Clock PLLs (Integrated Circuit Systems)
MK2049-34 - 3.3 V Communications Clock PLL (Integrated Circuit Systems)
MK2049-34A - 3.3 Volt Communications Clock VCXO PLL (Integrated Circuit Systems)
MK2049-35 - 3.3 V Communications Clock PLL (Integrated Circuit Systems)
MK2049-36 - 3.3 V Communications Clock PLL (Integrated Circuit Systems)

Other Datasheets by Renesas

Published: May 8, 2020 |