IDT5T9050 jr equivalent, 2.5v single data rate 1:5 clock buffer terabuffer jr.
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IDT5T9050
DESCRIPTION:
Optimized for 2.5V LVTTL Guaranteed Low Skew < 25ps (max) Very low duty cycle disto.
FUNCTIONAL BLOCK DIAGRAM
GL G
O U TPUT C O N TR O L
Q1
O U TPUT C O N TR O L
Q2
A
O U TPUT C O N TR O L
Q3
O U T.
Optimized for 2.5V LVTTL Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 300 (max) High speed propagation delay < 1.8ns. (max) Up to 200MHz operation Very low CMOS power levels Hot insertable and over-voltage tolerant inputs 1:5 f.
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