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Integrated Device Technology Electronic Components Datasheet

IDT5V2528 Datasheet

2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

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IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
2.5V / 3.3V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
INDUSTRIALTEMPERATURERANGE
IDT5V2528/A
FEATURES:
• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
• 1:10 fanout
• 3-level inputs for output control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Configurable 2.5V or 3.3V LVTTL outputs
• tPD Phase Error at 100MHz to 166MHz: ±150ps
• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
• Spread spectrum compatible
• Operating Frequency:
Std: 25MHz to 140MHz
A: 25MHz to 167MHz
• Available in TSSOP package
DESCRIPTION:
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
FUNCTIONAL BLOCK DIAGRAM
The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from
the 3.3V VDD and AVDD power supply pins.
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of
the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL
outputs. The number of 2.5V outputs is controlled by 3-level input signals
G_Ctrl and T_Ctrl, and by connecting the appropriate VDDQ pins to 2.5V or
3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input.
When the G_Ctrl input is mid or high, the outputs switch in phase and
frequency with CLK; when the G_Ctrl is low, all outputs (except FBOUT) are
disabled to the logic-low state.
Unlike many products containing PLLs, the IDT5V2528 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the IDT5V2528 requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for test purposes by strapping AVDD to ground.
28
G_Ctrl
T_Ctrl 1
MODE
SELECT
CLK 6
7
FBIN
AVDD
5
PLL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2002 Integrated Device Technology, Inc.
1
3
TY0, VDDQ pin 4
26
TY1, VDDQ pin 25
24
TY2, VDDQ pin 25
17
TY3, VDDQ pin 15
16
TY4, VDDQ pin 15
13
TY5, VDDQ pin 11
12
TY6, VDDQ pin 11
10
TY7, VDDQ pin 11
20
Y0, VDD pin 21
19
Y1, VDD pin 21
22
FBOUT, VDD pin 21
JUNE 2003
DSC 5971/11


Integrated Device Technology Electronic Components Datasheet

IDT5V2528 Datasheet

2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

No Preview Available !

IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
PIN CONFIGURATION
T_Ctrl
GND
TY0
VDDQ
AVDD
CLK
FBIN
AGND
GND
TY7
VDDQ
TY6
TY5
GND
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
TSSOP
TOP VIEW
G_Ctrl
GND
TY1
VDDQ
TY2
GND
FBOUT
VDD
Y0
Y1
GND
TY3
TY4
VDDQ
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max. Unit
VDD, VDDQ, AVDD Supply Voltage Range
–0.5 to +4.6
VI (2)
Input Voltage Range
–0.5 to +5.5
VO(2)
Voltage Range applied to any
–0.5 to
output in the HIGH or LOW state VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50
IOK
Output Clamp Current
±50
(VO < 0 or VO > VDD)
IO
Continuous Output Current
±50
(VO = 0 to VDD)
VDD or GND
Continuous Current
±200
TSTG StorageTemperatureRange –65 to +150
TJ
JunctionTemperature
+150
V
V
V
mA
mA
mA
mA
°C
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
CAPACITANCE(1)
Symbol
Description
Min Typ. Max.
CIN Input Capacitance
5
VI = VDD or GND
CO Output Capacitance
6
VI = VDD or GND
CL Load Capacitance 2.5V outputs 20
3.3V outputs 30
NOTE:
1. Unused inputs must be held HIGH or LOW to prevent them from floating.
Unit
pF
pF
pF
RECOMMENDED OPERATING RANGE
Symbol
VDD, AVDD (1)
VDDQ(1)
Description
Power Supply Voltage
Power Supply Voltage
TA AmbientOperatingTemperature
2.5V Outputs
3.3V Outputs
Min. Typ. Max.
3 3.3 3.6
2.3 2.5 2.7
3 3.3 3.6
–40 +25 +85
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
Unit
V
V
°C
2


Part Number IDT5V2528
Description 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
Maker Integrated Device
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IDT5V2528 Datasheet PDF






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