3.3v low skew pll clock driver.
* Eight zero delay outputs
* <250ps of output to output skew
* Selectable positive or negative edge synchronization
* Synchronous output enable
* Out.
It has eight zero delay LVTTL outputs.
When the GND/sOE pin is held low, all the outputs are synchronously enabled. How.
The IDT5V9910A is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications. It has eight zero delay LVTTL outputs.
When the GND/sOE pin is held low, all the outputs are synchronously e.
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