900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Integrated Device Technology Electronic Components Datasheet

IDT82V3012 Datasheet

T1/E1/OC3 WAN PLL

No Preview Available !

T1/E1/OC3 WAN PLL WITH DUAL
REFERENCE INPUTS
IDT82V3012
FEATURES
• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum
3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
• Supports ITU-T G.813 Option 1 clocks
• Supports ITU-T G.812 Type IV clocks
• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
• Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz
• Accepts two independent reference inputs which may have
same or different nominal frequencies applied to them
• Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o
output clock signals
• Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,
F32o, RSP and TSP
• Provides a C2/C1.5 output clock signal with the frequency
controlled by the selected reference input Fref0 or Fref1
• Holdover frequency accuracy of 0.025 ppm
• Phase slope of 5 ns per 125 µs
• Attenuates wander from 2.1 Hz
• Fast lock mode
• Provides Time Interval Error (TIE) correction
• MTIE of 600 ns
• JTAG boundary scan
• Holdover status indication
• Freerun status indication
• Normal status indication
• Lock status indication
• Input reference quality indication
• 3.3 V operation with 5 V tolerant I/O
• Package available: 56-pin SSOP (Green option available)
FUNCTIONAL BLOCK DIAGRAM
TDO TDI
OSCi TCLR RST
VDDD VSS VDDD VSS VDDD VSS VDDA VSS VDDA VSS
TCK
TMS
TRST
Fref0
Fref1
IN_sel
FLOCK
MON_out0
MON_out1
JTAG
OSC
Reference Input
Switch
TIE Control
Block
Virtual
Reference
Reference Input
Monitor 0
Reference Input
Monitor 1
Invalid Input
Signal Detection
DPLL
Feedback Signal
State Control Circuit
Frequency
Select Circuit 0
Frequency
Select Circuit 1
C2/C1.5
C32o
C19o
C19POS
C19NEG
C16o
C8o
C4o
C2o
C3o
C1.5o
C6o
F0o
F8o
F16o
F19o
F32o
RSP
TSP
LOCK
F0_sel0
F0_sel1
F1_sel0
F1_sel1
TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
1
February 6, 2009
DSC-6238/6


Integrated Device Technology Electronic Components Datasheet

IDT82V3012 Datasheet

T1/E1/OC3 WAN PLL

No Preview Available !

IDT82V3012
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
DESCRIPTION
The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference
inputs. It contains a Digital Phase-Locked Loop (DPLL), which
generates low jitter ST-BUS and 19.44 MHz clock and framing signals
that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz
input reference.
The IDT82V3012 provides 9 types of clock signals (C1.5o, C3o, C6o,
C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o,
F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3
links.
The IDT82V3012 is compliant with AT&T TR62411, Telcordia GR-
1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4, ETSI ETS
300 011, ITU-T G.813 Option 1, and ITU-T G.812 Type IV clocks. It
meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/
wander, frequency accuracy, capture range, phase change slope,
holdover frequency accuracy and MTIE (Maximum Time Interval Error)
requirements for these specifications.
The IDT82V3012 can be used in synchronization and timing control
for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse
source. It also can be used in access switch, access routers, ATM edge
switches, wireless base station controllers, or IADs (Integrated Access
Devices), PBXs, line cards and SONET/SDH equipments.
PIN CONFIGURATION
MODE_sel0
MODE_sel1
TCLR
RST
Fref0
Fref1
MON_out0
MON_out1
F0_sel0
F0_sel1
IN_sel
VSS
VDDD
C6o
C1.5o
C3o
C2o
VSS
VDDD
C4o
C19POS
C19NEG
C8o
C16o
C32o
VDDD
VSS
TCK
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 IDT82V3012 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
TIE_en
IC2
C2/C1.5
IC0
HOLDOVER
FREERUN
OSCi
F19o
VDDA
VSS
NORMAL
FLOCK
LOCK
C19o
TSP
RSP
F32o
F16o
VSS
VDDA
F8o
F1_sel0
F1_sel1
F0o
TDI
TMS
TRST
TDO
Figure - 1 IDT82V3012 SSOP56 Package Pin Assignment
Description
2 February 6, 2009


Part Number IDT82V3012
Description T1/E1/OC3 WAN PLL
Maker Integrated Device
Total Page 30 Pages
PDF Download

IDT82V3012 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 IDT82V3010 T1/E1/OC3 TELECOM CLOCK GENERATOR
Integrated Device Technology
2 IDT82V3011 T1/E1/OC3 WAN PLL
Integrated Device
3 IDT82V3012 T1/E1/OC3 WAN PLL
Integrated Device





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy