IDT82V3012 Description
The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/ wander, frequency accuracy, capture range, phase change slope,...
IDT82V3012 Key Features
- Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
- Supports ITU-T G.813 Option 1 clocks
- Supports ITU-T G.812 Type IV clocks
- Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface
- Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz
- Accepts two independent reference inputs which may have same or different nominal frequencies applied to them
- Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o, F32o, RSP and TSP
- Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1
- Holdover frequency accuracy of 0.025 ppm
- Phase slope of 5 ns per 125 µs