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IDTTM InterpriseTM Integrated Communications Processor
79RC32351
Features List
RC32300 32-bit Microprocessor – Enhanced MIPS-II ISA – Enhanced MIPS-IV cache prefetch instruction – DSP Instructions – MMU with 16-entry TLB – 8kB Instruction cache, 2-way set associative www.DataSheet4U.com – 2kB Data cache, 2-way set associative – Per line cache locking – Write-through and write-back cache management – Debug interface through the EJTAG port – Big or little endian support ◆ Interrupt Controller – Allows status of each interrupt to be read and masked ◆ UARTs – Two 16550 Compatible UARTs – Baud rate support up to 1.
79RC32351 Datasheet
