ICS831724I Key Features
- 2:1 differential clock/data multiplexer with fanout
- Two selectable, differential inputs
- Each differential input pair can accept the following levels: HCSL
- Four differential HCSL outputs
- Maximum input/output clock frequency: 350MHz
- Maximum input/output data rate: 700Mb/s (NRZ)
- LVCMOS interface levels for all control inputs
- PCI Express Gen 1,2,3 jitter pliant
- Input skew: 165ps (maximum)
- Output skew: 175ps (maximum)