ICS843002I-72 Datasheet PDF (FEMTOCLOCKS VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR) | Download Integrated Device Technology ICS843002I-72

ICS843002I-72 - FEMTOCLOCKS VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR

Description

The ICS843002I-72 is a member of the IC S HiperClockS™ family of high performance clock HiPerClockS™ solutions from IDT.

The ICS843002I-72 is a PLL based synchronous clock generator that is optimized for WCDMA channel card applications where jitter attenuation and frequency translation is needed.

Features

Two differential LVPECL outputs.
CLK input accepts the following input levels: LVCMOS or LVTTL levels.
Output frequency: 122.88MHz (typical).
FemtoClock VCO frequency range: 490MHz - 680MHz.
RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal (1.875MHz to 10MHz): 0.49ps (typical).
Deterministic jitter: 30fs (typical).
Random jitter, RMS: 2.2ps (typical).
Full 3.3V or mixed 3.3V core/2.5V output supply voltage.
-4.

Datasheet Details

Part number	ICS843002I-72
Manufacturer	Integrated Device Technology
File Size	329.67 KB
Description	FEMTOCLOCKS VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
Datasheet	ICS843002I-72 Datasheet
Additional preview pages of the ICS843002I-72 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR ICS843002I-72 GENERAL DESCRIPTION The ICS843002I-72 is a member of the IC S HiperClockS™ family of high performance clock HiPerClockS™ solutions from IDT. The ICS843002I-72 is a PLL based synchronous clock generator that is optimized for WCDMA channel card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the second PLL stage.

Published: Mar 27, 2010 |