ICS854S204I Overview
The ICS854S204I is a low skew, high performance IC S dual, programmable 1-to-2 Differential-to-LVDS, HiPerClockS™ LVPECL Fanout Buffer and a member of the HiPerClock S™ family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels.
ICS854S204I Key Features
- Two programmable differential LVDS or LVPECL output banks
- Two differential clock input pairs
- PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML
- Maximum output frequency: 3GHz
- Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx inputs
- Output skew: 15ps (maximum)
- Bank skew: 15ps (maximum)
- Propagation delay: 500ps (maximum)
- Additive phase jitter, RMS: 0.15ps (typical)
- Full 3.3V or 2.5V power supply