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* Guaranteed low skew: <50ps (maximum) Very low duty cycle distortion: <100ps (maximum High sp.

* Clock distribution Pin Assignment GND PD FSEL VDD Q1 Q1 Q2 Q2 VDD SEL G GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 2.

The IDT5T93GL04 2.5V differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distributio.

IDT5T93GL02

IDT5T93GL06

IDT5T93GL10

IDT5T9306

IDT5T9310

IDT5T9316

IDT5T905

IDT5T9050

IDT5T907

IDT5T9070

IDT5T915

IDT5T929

IDT5T940