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IDT7280 Datasheet

CMOS DUAL ASYNCHRONOUS FIFO

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CMOS DUAL ASYNCHRONOUS FIFO
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
IDT7280
IDT7281
IDT7282
IDT7283
IDT7284
IDT7285
FEATURES:
The IDT7280 is equivalent to two IDT7200 256 x 9 FIFOs
The IDT7281 is equivalent to two IDT7201 512 x 9 FIFOs
The IDT7282 is equivalent to two IDT7202 1,024 x 9 FIFOs
The IDT7283 is equivalent to two IDT7203 2,048 x 9 FIFOs
The IDT7284 is equivalent to two IDT7204 4,096 x 9 FIFOs
The IDT7285 is equivalent to two IDT7205 8,192 x 9 FIFOs
Low power consumption
— Active: 685 mW (max.)
— Power-down: 83 mW (max.)
Ultra high speed—12 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bi-directional, width expansion, depth expansion,
bus-matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CMOS technology
Space-saving TSSOP
Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional
and compatible to two IDT7200/7201/7202/7203/7204/7205 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimited expansion capability in both
word size and depth.
The reads and writes are internally sequential through the use of ring pointers,
with no address information required to load and unload data. Data is toggled
in and out of the devices through the use of the Write (W) and Read (R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when RT is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They are
designed for those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
DA(DTAA0IN-DPAU8T) S
RSA
WA
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY A
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
THREE-
STATE
BUFFERS
RA READ
CONTROL
FLAG
LOGIC
EXPANSION
LOGIC
RESET
LOGIC
XIA
XOA/HFA FFA EFA
DATA
FLA/RTA
OUTPUTS
(QA0-QA8)
WB
WRITE
CONTROL
DA(DTAB0IN-DPBU8T) S
RSB
WRITE
POINTER
THREE-
STATE
BUFFERS
RAM
ARRAY B
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
READ
CONTROL
FLAG
LOGIC
EXPANSION
LOGIC
RB XIB
XOB/HFB
FFB EFB
DATA
OUTPUTS
(QB0-QB8)
RESET
LOGIC
FLB/RTB
3208 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2017
DSC-3208/10


Integrated Device Technology Electronic Components Datasheet

IDT7280 Datasheet

CMOS DUAL ASYNCHRONOUS FIFO

No Preview Available !

IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALTEMPERATURERANGE
PIN CONFIGURATION
FFA
QA0
QA1
QA2
QA3
QA8
GND
RA
QA4
QA5
QA6
QA7
XOA/HFA
EFA
FFB
QB0
QB1
QB2
QB3
QB8
GND
RB
QB4
QB5
QB6
QB7
XOB/HFB
EFB
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
TSSOP (SO56-2, order code: PA)
TOP VIEW
XIA
DA0
DA1
DA2
DA3
DA8
WA
VCC
DA4
DA5
DA6
DA7
FLA/RTA
RSA
XIB
DB0
DB1
DB2
DB3
DB8
WB
VCC
DB4
DB5
DB6
DB7
FLB/RTB
RSB
3208 drw 02
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Com'l & Ind'l
Unit
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
V
TSTG StorageTemperature
IOUT DC Output Current
–55 to +125
–50 to +50
°C
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min. Typ. Max.
VCC Supply Voltage
4.5 5.0 5.5
GND Supply Voltage
0 00
VIH(1) Input High Voltage
2.0 — —
VIL(2) Input Low Voltage
— — 0.8
TA OperatingTemperature
Commercial
0 — 70
TA OperatingTemperature
Industrial
–40 — 85
NOTES:
1. For RT/RS/XI input, VIH = 2.6V (commercial).
2. 1.5V undershoots are allowed for 10ns once per cycle.
Unit
V
V
V
V
°C
°C
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
IDT7280L
IDT7283L
IDT7281L
IDT7282L
IDT7284L
IDT7285lL
Commercial & Industrial(1)
Commercial & Industrial(1)
tA = 12, 15 ns
tA = 12, 15 ns
Symbol
ILI(2)
ILO(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Min. Max. Min. Max.
–1 1 –1 —
–10 10 –10 10
VOH Output Logic “1” Voltage IOH = –2mA
2.4
2.4
VOL
ICC1(4,5)
ICC2(4,7)
Output Logic “0” Voltage IOL = 8mA
Active Power Supply Current (both FIFOs)
Standby Current (R=W=RS=FL/RT=VIH)
0.4
125(6)
15
0.4
150
15
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard
device.
2. Measurements with 0.4 VIN VCC.
3. R VIH, 0.4 VOUT VCC.
4. Tested with outputs open (IOUT = 0).
5. Tested at f = 20 MHz.
6. Typical ICC1 = 2*[15 + 2*fS + 0.02*CL*fS] (in mA) with VCC = 5V, TA = 25oC, fS = WCLK
frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V.
AC TEST CONDITIONS
Input Pulse Levels
InputRise/Fall Times
Input Timing Reference Levels
Output Reference Levels
OutputLoad
5V
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
Unit
μA
μA
V
V
mA
mA
CAPACITANCE (TA = +25oC, f = 1.0 MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Condition
VIN = 0V
VOUT = 0V
NOTE:
1. Characterized values, not currently tested.
Max.
8
8
Unit
pF
pF
2
TO
OUTPUT
PIN
680Ω
1.1K
30pF*
3208 drw 03
or equivalent circuit
Figure 1. Output Load
* Includes scope and jig capacitances.
JUNE 29, 2012


Part Number IDT7280
Description CMOS DUAL ASYNCHRONOUS FIFO
Maker Integrated Device Technology
Total Page 12 Pages
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