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IDT72821 Datasheet

DUAL CMOS SyncFIFO

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DUAL CMOS SyncFIFO™
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
IDT72851
FEATURES:
The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs
The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs
The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs
The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs
The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs
The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
Ideal for prioritization, bidirectional, and width expansion
applications
10 ns read/write cycle time for the IDT72801/72811/72821/72831/
72841/72851
Separate control lines and data lines for each FIFO
Separate Empty, Full, Programmable Almost-Empty and Almost-
Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin
Quad Flatpack (STQFP)
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72801/72811/72821/72831/72841/72851 are dual synchronous
(clocked)FIFOs. ThedeviceisfunctionallyequivalenttotwoIDT72201/72211/
72221/72231/72241/72251 FIFOs in a single package with all associated
control, data, and flag lines assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0
- DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each
input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write
Enable pins (WENA1, WENA2, WENB1, WENB2). Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate write enable pins are asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,
RENB2). The Read Clock can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual clock operation.
An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO
for three-state output control.
EachofthetwoFIFOshastwofixedflags,Empty(EFA, EFB)andFull(FFA,
FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full
(PAFA, PAFB), are provided for each FIFO bank to improve memory utilization.
If not programmed, the programmable flags default to empty+7 for PAEAand
PAEB, and full-7 for PAFA and PAFB.
The IDT72801/72811/72821/72831/72841/72851 architecture lends itself
to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion
These FIFOs is fabricated using high-performance submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA1
WENA2
DA0 - DA8
EFA
PAEA
LDA
PAFA
FFA
WCLKB
WENB1
WENB2
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
OUTPUT REGISTER
RESET LOGIC
DB0 - DB8
INPUT REGISTER
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
OUTPUT REGISTER
LDB
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
EFB
PAEB
PAFB
FFB
RSA
OEA
QA0 - QA8
RCLKA
RENA1
RENA2
RSB OEB QB0 - QB8
IDT, IDT logo and the SyncFIFO logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
1
©2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RCLKB
RENB1
RENB2
3034 drw 01
FEBRUARY 2018
DSC-3034/7


Integrated Device Technology Electronic Components Datasheet

IDT72821 Datasheet

DUAL CMOS SyncFIFO

No Preview Available !

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
PIN CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
QA1
QA2
QA3
QA4
QA5
QA6
QA7
QA8
VCC
WENA2/LDA
WCLKA
WENA1
RSA
DA8
DA7
DA6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48 QB0
47 FFB
46 EFB
45 OEB
44 RENB2
43
42
RCLKB
RENB1
41 GND
40
39
38
VCC
PAEB
PAFB
37 DB0
36 DB1
35 DB2
34 DB3
33 DB4
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
3034 drw 02
2 MARCH 2013


Part Number IDT72821
Description DUAL CMOS SyncFIFO
Maker Integrated Device Technology
Total Page 16 Pages
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