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Integrated Device Technology Electronic Components Datasheet

IDT72V16160 Datasheet

3.3V MULTIMEDIA FIFO 16 BIT V-III/ 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY

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3.3V MULTIMEDIA FIFO
16 BIT V-III, 32 BIT Vx-III FAMILY
UP TO 1 Mb DENSITY
IDT72V15160
IDT72V16160
IDT72V17160
IDT72V18160
IDT72V19160
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
FEATURES:
Choose among the following memory organizations: Commercial
V-III
IDT72V15160 - 4,096 x 16
IDT72V16160 - 8,192 x 16
IDT72V17160 - 16,384 x 16
IDT72V18160 - 32,768 x 16
IDT72V19160 - 65,536 x 16
Vx-III
IDT72V14320 - 1,024 x 32
IDT72V15320 - 2,048 x 32
IDT72V16320 - 4,096 x 32
IDT72V17320 - 8,192 x 32
IDT72V18320 - 16,384 x 32
IDT72V19320 - 32,768 x 32
Up to 100 MHz Operation of the Clocks
5V input tolerant
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags through serial input
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function (PBGA Only)
Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III)
Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid
Array (PBGA) (with additional features)
Industrial temperature range (–40°C to +85°C)
High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
*Available on the Vx-III PBGA package only.
WCLK
WEN
D0 - Dn
Data In
x16, x32
TCK
*TRST
* TMS
* TDI
**TDO
WRITE
CONTROL
MRS PRS
RESET LOGIC
READ
CONTROL
FIFO ARRAY
JTAG CONTROL
(BOUNDARY
SCAN)
*
FLAG LOGIC
LD SI FSEL1 EF
HF FF
SEN PFM FSEL0
PAE PAF
RCLK
REN
OE
Q0 - Qn
Data Out
x16, x32
6163 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-6163/2


Integrated Device Technology Electronic Components Datasheet

IDT72V16160 Datasheet

3.3V MULTIMEDIA FIFO 16 BIT V-III/ 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY

No Preview Available !

IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
DESCRIPTION:
The IDT V-III and Vx-III Multimedia FIFOs are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with independent clocked
read and write controls and high density offerings up to 1 Mbit.
Each FIFO has a data input port (Dn) and a data output port (Qn). The
frequencies of both the RCLK (read port clock) and the WCLK (write port
clock) signals may vary from 0 to fS(MAX) with complete independence.
There are no restrictions on the frequency oftheoneclockinputwithrespect
to the other.
These FIFOs have five flag pins,EF (Empty Flag),FF (FullFlag),HF(Half-
full Flag), PAE(Programmable Almost-Empty flag) and PAF(Programmable
Almost-Full flag).
PAE and PAFcan be programmed independently to switch at any point in
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
be loaded with the serial interface to any user desired value or by default values.
Eight default offset settings are provided, so thatPAEcan be set to switch at a
predefined number of locations from the empty boundary and the PAF threshold
canalsobesetatsimilarpredefinedvaluesfromthefullboundary. Thedefault
offset values are set during Master Reset by the state of the FSEL0, FSEL1, and
LD pins.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI).
During Master Reset (MRS) the read and write pointers are set to the first
location of the FIFO.
PIN CONFIGURATIONS (16-BIT V-III FAMILY)
INDEX
WEN
SEN
DNC(1)
VCC
DNC(1)
GND
GND
D0
VCC
D1
GND
D2
D3
GND
D4
D5
D6
D7
D8
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NOTE:
1. DNC = Do Not Connect.
60 VCC
59 OE
58 VCC
57 Q0
56 Q1
55 GND
54 GND
53 DNC(1)
52 Q2
51 VCC
50 Q3
49 Q4
48 GND
47 Q5
46 GND
45 Q6
44 VCC
43 Q7
42 Q8
41 Q9
6163 drw02
TQFP (PN80-1, order code: PF)
TOP VIEW
2


Part Number IDT72V16160
Description 3.3V MULTIMEDIA FIFO 16 BIT V-III/ 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY
Maker Integrated Device Technology
Total Page 26 Pages
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