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Integrated Device Technology Electronic Components Datasheet

IDT72V11165 Datasheet

3.3 VOLT MULTIMEDIA FIFO 256 x 16/ 512 x 16/ 1/024 x 16/ 2/048 x 16/ and 4/096 x 16

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3.3 VOLT MULTIMEDIA FIFO
256 x 16, 512 x 16,
1,024 x 16, 2,048 x 16,
and 4,096 x 16
IDT72V11165, IDT72V12165
IDT72V13165, IDT72V14165
IDT72V15165
FEATURES
256 x 16-bit organization array (IDT72V11165)
512 x 16-bit organization array (IDT72V12165)
1,024 x 16-bit organization array (IDT72V13165)
2,048 x 16-bit organization array (IDT72V14165)
4,096 x 16-bit organization array (IDT72V15165)
15 ns read/write cycle time
5V input tolerant
Independent Read and Write Clocks
Empty/Full and Half-Full flag capability
Output enable puts output data bus in high-impedance state
Available in a 64-lead thin quad flatpack (10x10mm and 14x14mm
TQFP)
Industrial temperature range (–40°C to +85°C)
DESCRIPTION
The IDT72V11165/72V12165/72V13165/72V14165/72V15165 devices
are First-In, First-Out (FIFO) memories with clocked read and write controls.
TheseFIFOshave16-bitinputandoutputports. Theinputportiscontrolled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is written
into the Multimedia FIFO on every clock when WEN is asserted. The output port
is controlled by another clock pin (RCLK) and another enable pin (REN). The
Read Clock (RCLK) can be tied to the Write Clock for single clock operation or
the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
These Multimedia FIFOs support three fixed flags: Empty Flag (EF), Full
Flag (FF), and Half Full Flag (HF).
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN
WRITE
CONTROL
D0 - D15
Data In
x16
FIFO ARRAY
RESET LOGIC
RS
READ
CONTROL
RCLK
REN
OE
Q0 - Q15
Data Out
x16
FLAG OUTPUTS
EF HF FF
6359 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-6359/2


Integrated Device Technology Electronic Components Datasheet

IDT72V11165 Datasheet

3.3 VOLT MULTIMEDIA FIFO 256 x 16/ 512 x 16/ 1/024 x 16/ 2/048 x 16/ and 4/096 x 16

No Preview Available !

IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
PIN CONFIGURATIONS
PIN 1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
INDUSTRIAL
TEMPERATURERANGE
Q2
Q3
GND
Q4
Q5
VCC
Q6
Q7
GND
Q8
Q9
Q10
Q11
GND
Q12
VCC
NOTE:
1. DNC = Do Not Connect.
STQFP (PP64-1, order code: TF)
TOP VIEW
6359 drw02
PIN DESCRIPTION
Symbol
Name
I/O
Description
D0–D15
EF
FF
HF
OE
Data Inputs
Empty Flag
Full Flag
Half-Full Flag
Output Enable
I Data inputs for an 16-bit bus.
O EF indicates whether or not the FIFO memory is empty.
O FF indicates whether or not the FIFO memory is full.
O The device is more than half full when HF is LOW.
I When OE is LOW, the data output bus is active. IfOE is HIGH, the output data bus will be in a high-impedance
state.
Q0–Q15
RCLK
REN
Data Outputs
Read Clock
Read Enable
RS Reset
WCLK
WEN
Write Clock
Write Enable
O Data outputs for an 16-bit bus.
I When RENis LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
I WhenREN isLOW,dataisreadfromtheFIFOoneveryLOW-to-HIGHtransitionofRCLK. WhenRENisHIGH,
the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW.
I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF
goes HIGH, and EF goes LOW. A reset is required before an initial WRITE after power-up.
I When WENis LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
I When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
VCC Power
I +3.3V power supply pins.
GND Ground
I Ground pins.
2


Part Number IDT72V11165
Description 3.3 VOLT MULTIMEDIA FIFO 256 x 16/ 512 x 16/ 1/024 x 16/ 2/048 x 16/ and 4/096 x 16
Maker Integrated Device Technology
Total Page 8 Pages
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