IDT72V10081 Datasheet | Integrated Device Technology

3.3 VOLT MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, and 4,096 x 8 IDT72V10081, IDT72V11081 IDT72V12081, IDT72V13081 IDT72V14081 Features - - - - - - - - - - - - DESCRIPTION The IDT72V10081/72V11081/72V12081/72V13081/72V14081 devices are low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These devices have a 256, 512, 1,024, 2,048 and 4,096 x 8-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs such as graphics and interprocessor munication. These FIFOs have 8-bit input and output ports. The input port is controlled by a free-running clock (WCLK) and Write Enable pin (WEN). Data is written into the Multimedia FIFO on every rising clock edge when the Write Enable pin is asserted. The output port is controlled by another clock pin (RCLK) and Read Enable pin (REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE ) is provided on the read port for three-state control of the output. The Multimedia FIFOs have two fixed flags, Empty (EF) and Full (FF). These FIFOs are fabricated using IDT's submicron CMOS technology. 256 x 8-bit organization array (IDT72V10081) 512 x 8-bit organization array (IDT72V11081) 1,024 x 8-bit organization array (IDT72V12081) 2,048 x 8-bit organization array (IDT72V13081) 4,096 x 8-bit organization array (IDT72V14081) 15 ns read/write cycle time 5V input tolerant Independent Read and Write clocks Empty and Full Flags signal FIFO status Output Enable puts output data bus in high-impedance state Available in 32-pin plastic Thin Quad Flat Pack (TQFP) Industrial temperature range (- 40°C to +85° C) FUNCTIONAL BLOCK DIAGRAM WCLK WEN WRITE CONTROL READ CONTROL RCLK REN FIFO ARRAY D0 - D7 Data In x8 OE Q0 - Q 7 Data Out x8 RESET LOGIC FLAG OUTPUTS 6161 drw01 IDT and the IDT logo are registered trademarks...