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IDT72V11165 - 3.3 VOLT MULTIMEDIA FIFO 256 x 16/ 512 x 16/ 1/024 x 16/ 2/048 x 16/ and 4/096 x 16

Datasheet Summary

Description

The IDT72V11165/72V12165/72V13165/72V14165/72V15165 devices are First-In, First-Out (FIFO) memories with clocked read and write controls.

These FIFOs have 16-bit input and output ports.

The input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN).

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Datasheet Details

Part number IDT72V11165
Manufacturer Integrated Device Technology
File Size 123.31 KB
Description 3.3 VOLT MULTIMEDIA FIFO 256 x 16/ 512 x 16/ 1/024 x 16/ 2/048 x 16/ and 4/096 x 16
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3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16 IDT72V11165, IDT72V12165 IDT72V13165, IDT72V14165 IDT72V15165 FEATURES • • • • • • • • • • • • DESCRIPTION The IDT72V11165/72V12165/72V13165/72V14165/72V15165 devices are First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs have 16-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is written into the Multimedia FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and another enable pin (REN). The Read Clock (RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.
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