IDT72V11165 Overview
These FIFOs have 16-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is written into the Multimedia FIFO on every clock when WEN is asserted.
IDT72V11165 Key Features
- DESCRIPTION
- D15 Data In x16
- Q15 Data Out x16