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Integrated Device Technology Electronic Components Datasheet

IDT72V3631 Datasheet

(IDT72V36x1) 3.3 VOLT CMOS SyncFIFOTM

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3.3 VOLT CMOS SyncFIFOTM
512 x 36
1,024 x 36
2,048 x 36
IDT72V3631
IDT72V3641
IDT72V3651
FEATURES
Storage capacity:
IDT72V3631 - 512 x 36
IDT72V3641 - 1,024 x 36
IDT72V3651 - 2,048 x 36
Supports clock frequencies up to 67 MHz
Fast access times of 10ns
Free-running CLKA and CLKB can be asynchronous or coinci-
dent (permits simultaneous reading and writing of data on a
single clock edge)
Clocked FIFO buffering data from Port A to Port B
Synchronous read retransmit capability
Mailbox register in each direction
Programmable Almost-Full and Almost-Empty flags
Microprocessor interface control logic
Input Ready (IR) and Almost-Full (AF) flags synchronized by
CLKA
Output Ready (OR) and Almost-Empty (AE) flags synchronized
by CLKB
Available in 132-pin plastic quad flat package (PQFP) or space-
saving 120-pin thin quad flat package (TQFP)
Pin and functionally compatible versions of the 5V operating
IDT723631/723641/723651
Easily expandable in width and depth
Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION
The IDT72V3631/72V3641/72V3651 are pin and functionally compatible
versons of the IDT723631/723641/723651, designed to run off a 3.3V supply
forexceptionallylow-powerconsumption. Thesedevicesaremonolithichigh-
speed,low-power,CMOSclockedFIFOmemory. Itsupportsclockfrequencies
upto67MHzandhasreadaccesstimesasfastas10ns. The512/1,024/2,048
x36dual-portSRAMFIFObuffersdatafromportAtoPortB. TheFIFOmemory
has retransmit capability, which allows previously read data to be accessed
again. The FIFO operates in First Word Fall Through mode and has flags to
indicate empty and full conditions and conditions and two programmable flags
(Almost-Full and Almost-Empty)to indicate when a selectednumber ofwords
is stored in memory. Communication between each port may take place with
FUNCTIONAL BLOCK DIAGRAM
MBF1
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST
Reset
Logic
Mail 1
Register
RAM ARRAY
512 x 36
1,024 x 36
2,048 x 36
RTM
A0 - A35
IR
AF
36
Write Read
Pointer Pointer
Status Flag
Logic
RFM
B0 - B35
OR
AE
FS0/SD
FS1/SEN
Flag Offset
Registers
10
Mail 2
Register
MBF2
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
11
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
4658 drw 01
NOVEMBER 2003
DSC-4658/1


Integrated Device Technology Electronic Components Datasheet

IDT72V3631 Datasheet

(IDT72V36x1) 3.3 VOLT CMOS SyncFIFOTM

No Preview Available !

IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
DESCRIPTION (CONTINUED)
two 36-bit mailbox registers. Each mailbox register has a flag to signal when
new mwwaiwl h.aDsabtaeeSnhseteotr4eUd. cTowmo or more devices may be used in parallel to create
wider data paths. Expansion is also possible in word depth.
These devices are a clocked FIFO, which means each port employs a
synchronousinterface. AlldatatransfersthroughaportaregatedtotheLOW-
to-HIGH transition of a continuous (free-running) port clock by enable signals.
The continuous clocks for each port are independent of one another and can
be asynchronous or coincident. The enables for each port are arranged to
provide a simple interface between microprocessors and/or buses with
synchronous control.
The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are two-stage
synchronized to CLKA. The Output Ready (OR) flag and Almost-Empty (AE)
flag of the FIFO are two-stage synchronized to CLKB. Offset values for the
Almost-Full and Almost-Empty flags of the FIFO can be programmed from port
A or through a serial input.
The IDT72V3631/72V3641/72V3651 are characterized for operation from
0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by
specialorder. ThesedevicesarefabricatedusingIDT'shighspeed,submicron
CMOS technology.
PIN CONFIGURATION
NC
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
NC
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
*
*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
NOTES:
1. NC – No internal connection.
2. Uses Yamaichi socket IC51-1324-828.
PQFP (PQ132-1, order code: PQF)
TOP VIEW
2
116 NC
115 NC
114 A35
113 A34
112 A33
111 A32
110 VCC
109 A31
108 A30
107 GND
106 A29
105 A28
104 A27
103 A26
102 A25
101 A24
100 A23
99 GND
98 A22
97 VCC
96 A21
95 A20
94 A19
93 A18
92 GND
91 A17
90 A16
89 A15
88 A14
87 A13
86 VCC
85 A12
84 NC
4658 drw 02


Part Number IDT72V3631
Description (IDT72V36x1) 3.3 VOLT CMOS SyncFIFOTM
Maker Integrated Device Technology
Total Page 21 Pages
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