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IDT74LVC16373A Datasheet

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

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IDT74LVC16373A
3.3VCMOS16-BIT TRANSPARENT D-TYPE LATCH
INDUSTRIALTEMPERATURERANGE
3.3V CMOS 16-BIT
TRANSPARENT D-TYPE
LATCH WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
IDT74LVC16373A
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The LVC16373A 16-bit transparent D-type latch is built using advanced
dual metal CMOS technology. This high-speed, low-power latch is ideal
for temporary storage of data. The LVC16373A can be used for implement-
ing memory address latches, I/O ports, and bus drivers. The Output Enable
and Latch Enable controls are organized to operate each device as two 8-
bit latches or one 16-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
All pins of the LVC16373A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
The LVC16373A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
1OE 1
1LE 48
1D1 47
D
CQ
2OE 24
2 1Q1
2LE 25
2D1 36
D
CQ
13 2Q1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
IDT and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2015 Integrated Device Technology, Inc.
1
JULY 2015
DSC-4624/6


Integrated Device Technology Electronic Components Datasheet

IDT74LVC16373A Datasheet

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

No Preview Available !

IDT74LVC16373A
3.3VCMOS16-BIT TRANSPARENT D-TYPE LATCH
PIN CONFIGURATION
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
SSOP/ TSSOP
TOP VIEW
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
INDUSTRIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5
TSTG Storage Temperature
–65 to +150
IOUT DC Output Current
–50 to +50
IIK Continuous Clamp Current,
IOK VI < 0 or VO < 0
–50
ICC Continuous Current through each
ISS VCC or GND
±100
Unit
V
°C
mA
mA
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
4.5
6 pF
COUT
Output Capacitance VOUT = 0V
6.5
8
pF
CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
Description
xDx Data Inputs
xLE Latch Enable Input (Active HIGH)
xOE Output Enable Inputs (Active LOW)
x Q x 3-State Outputs
FUNCTION TABLE(1)
Inputs
Outputs
xDx xLE xOE
xQx
HH L H
LH
L
L
XL
L Q(2)
XX H
Z
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
2


Part Number IDT74LVC16373A
Description 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
Maker Integrated Device Technology
Total Page 6 Pages
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