IDTCSPF2510C driver equivalent, 3.3v phase-lock loop clock driver.
* Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
* Distributes one clock input to one bank of ten outputs
* Output enable bank control.
* Distributes one clock input to one bank of ten outputs
* Output enable bank control
* External feedback (F.
The IDTCSPF2510C is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both
frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically design.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 100.89KB)