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* 4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band.

KEY SPECIFICATION:
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* CPU/SRC CLK cycle to cycle jitter < 125ps SATA CLK cycle to cycle jitter < 125ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error as low as 36 ppm FUNCTIONAL BLOCK DIAGRAM DataShee.

IDTCV104B

IDTCV105E

IDTCV109E

IDTCV110J

IDTCV110L

IDTCV115C

IDTCV119E

IDTCV122C

IDTCV123

IDTCV125

IDTCV140

IDTCV144

IDTCV145