Datasheet4U Logo Datasheet4U.com

IS49NLC18320 - Common I/O RLDRAM 2 Memory

Download the IS49NLC18320 datasheet PDF (IS49NLC96400 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for common i/o rldram 2 memory.

Description

1.1 576Mb (64Mx9) Common I/O BGA Ball‐out (Top View)  1 A VREF B VDD C VTT D A221 E A21 F A5 G A8 H BA2 J NF2 K DK L REF# M WE# N A18 P A15 R VSS T VTT U VDD V VREF 2 VSS DNU3 DNU3 DNU3 DNU3 DNU3 A6 A9 NF2 DK# CS# A16 DNU3 DNU3 DNU3 DNU3 DNU3 ZQ 3 VEXT DNU3 DNU3 DNU3 DNU3 DNU3 A7 VSS VDD VDD VSS

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS49NLC96400-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • IS49NLC18160A - Common I/O RLDRAM 2 Memory (ISSI)
  • IS49NLC36800A - Common I/O RLDRAM 2 Memory (ISSI)
  • IS49NLC93200A - Common I/O RLDRAM 2 Memory (ISSI)
  • IS49RL18128 - 4 Meg x 18 x 16 Banks x 2 Ranks RLDRAM3 (ISSI)
  • IS49RL36640 - 2Meg x 36 x 16 Banks RLDRAM3 (ISSI)
  • IS41C16128 - 128K x 16 (2-MBIT) DYNAMIC RAM (ISSI)
  • IS41C16256 - 256K x 16 (4-MBIT) DYNAMIC RAM (ISSI)
  • IS41C16257 - 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE (Integrated Silicon Solution Inc)
  • IS41C8512 - 512K x 8 (4-MBIT) DYNAMIC RAM (Integrated Circuit Solution)
  • IS41LV16256 - 256K x 16 (4-MBIT) DYNAMIC RAM (ISSI)
Other Datasheets by Integrated Silicon Solution

Full PDF Text Transcription

Click to expand full text
IS49NLC96400,IS49NLC18320,IS49NLC36160 576Mb (x9, x18, x36) Common I/O RLDRAM 2 Memory    FEATURES ADVANCED INFORMATION JULY 2012  533MHz DDR operation (1.067 Gb/s/pin data  rate)   38.4Gb/s peak bandwidth (x36 at 533 MHz  clock frequency)   Reduced cycle time (15ns at 533MHz)   32ms refresh (16K refresh for each bank; 128K  refresh command must be issued in total each  32ms)   8 internal banks   Non‐multiplexed addresses (address  multiplexing option available)   SRAM‐type interface   Programmable READ latency (RL), row cycle  time, and burst sequence length   Balanced READ and WRITE latencies in order to  optimize data bus utilization   Data mask signals (DM) to mask signal of  WRITE data; DM is sampled on both edges of  DK.
Published: |