IS61DDB21M36 srams equivalent, ddr-ii (burst of 2) cio synchronous srams.
* 1M x 36 or 2M x 18.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Common data input/output bus.
* Synchronous pipeline read with self-.
The 36Mb IS61DDB21M36 and IS61DDB22M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations ar.
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