IS61DDB21M36A
FEATURES
- 1Mx36 and 2Mx18 configuration available.
- On-chip delay-locked loop (DLL) for wide data valid window.
- mon I/O read and write ports.
- Synchronous pipeline read with self-timed late write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- Fixed 2-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only.
- Two input clocks (C and C#) for data output control.
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
- +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.
- HSTL input and output interface.
- Registered addresses, write and read controls, byte writes, data in, and data outputs.
- Full data coherency.
- Boundary scan using limited set of JTAG 1149.1 functions.
- Byte write capability.
- Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
- Programmable...
