IS61DDB21M18A - 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM

Product Overview

Integrated Silicon Solution

Part number	IS61DDB21M18A
Manufacturer	Integrated Silicon Solution
File Size	589.81 KB
Description	18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
Datasheet	IS61DDB21M18A Datasheet
Additional preview pages of the IS61DDB21M18A datasheet.

The 18Mb IS61DDB251236A and IS61DDB21M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

512Kx36 and 1Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two input clocks (C and C#.

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Published: Jul 25, 2016 |