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IS61DDB42M36 Datasheet DDR-II (Burst of 4) CIO Synchronous SRAMs

Manufacturer: ISSI (now Infineon)

Download the IS61DDB42M36 datasheet PDF. This datasheet also includes the IS61DDB44M18 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (IS61DDB44M18-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

General Description

The 72Mb IS61DDB42M36 and IS61DDB44M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Overview

I7D7D2DMR-bII (2M x 36 & 4M x (Burst o.

f 4) CIO 18) Synchronous SRAMs A MAY.

Key Features

  • 2M x 36 or 4M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with late write operation.
  • Double data rate (DDR-II) interface for read and write input ports.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges only.
  • Two input clocks (C an.

More Datasheets from ISSI (now Infineon)

Part Number Description
IS61DDB42M36A 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB42M18 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M18A 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M18A 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M36 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB41M36A 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB44M18 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB44M18A 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB451236A 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB21M18A 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM