IS61NLF51236 Overview
100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single Read/Write control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control us- ing MODE input Three chip enables for simple depth expansion and address pipelining Power Down mode mon data inputs and data outputs CKE pin to enable clock...
IS61NLF51236 Key Features
- 100 percent bus utilization
- No wait cycles between Read and Write
- Internal self-timed write cycle
- Individual Byte Write Control
- Single Read/Write control pin
- Clock controlled, registered address
- Interleaved or linear burst sequence control us
- Three chip enables for simple depth expansion
- Power Down mode
- mon data inputs and data outputs