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Integrated Silicon Solution Electronic Components Datasheet

IS61VF51232 Datasheet

512K x 32 Synchronous Flow-through Static RAM

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ISSIIS61VF51232 IS61VF51236 IS61VF10018
®
512K x 32, 512K x 36, 1024K x 18
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
ADVANCE INFORMATION
October 2001
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE input
• Three chip enable option for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +2.5V, ±5% operation
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
DESCRIPTION
The ISSI IS61VF51232, IS61VF51236, and IS61VF10018
are high-speed, low-power synchronous static RAMs de-
signed to provide burstable, high-performance memory for
communication and networking applications. The
IS61VF51232 is organized as 524,288 words by 32 bits and
the IS61VF51236 is organized as 524,288 words by 36
bits. The IS61VF10018 is organized as 1,048,576 words
by 18 bits. Fabricated with ISSI's advanced CMOS
technology, the device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit. All synchronous inputs
pass through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
www.DataSheet4U.com
Parameter
Clock Access Time
Cycle Time
Frequency
-7.5 -8.5
7.5 8.5
8 10
125 100
Units
ns
ns
MHz
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
10/23/01
1


Integrated Silicon Solution Electronic Components Datasheet

IS61VF51232 Datasheet

512K x 32 Synchronous Flow-through Static RAM

No Preview Available !

IS61VF51232 IS61VF51236 IS61VF10018
ISSI®
BLOCK DIAGRAM
CLK
ADV
ADSC
ADSP
A
19/20
GW
BWE
BWd
(x32/x36)
BWc
(x32/x36)
BWb
(x32/x36/x18)
BWa
(x32/x36/x18)
CE
CE2
CE2
MODE
CLK Q0
BINARY
COUNTER
CE Q1
A0
A1
CLR
A0'
A1'
DQ
ADDRESS
REGISTER
CE
CLK
17/18
512Kx32; 512Kx36;
1024Kx18
MEMORY ARRAY
19/20
32, 36,
or 18
32, 36,
or 18
D DQd Q
BYTE WRITE
REGISTERS
CLK
D DQc Q
BYTE WRITE
REGISTERS
CLK
D DQb Q
BYTE WRITE
REGISTERS
CLK
D DQa Q
BYTE WRITE
REGISTERS
CLK
DQ
ENABLE
REGISTER
CE
CLK
4
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
32, 36,
or 18
DQa - DQd
OE
www.DataSheet4U.com
OE
2
DQ
ENABLE
DELAY
REGISTER
CLK
Integrated Silicon Solution, Inc. 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
10/23/01


Part Number IS61VF51232
Description 512K x 32 Synchronous Flow-through Static RAM
Maker Integrated Silicon Solution
Total Page 24 Pages
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