Datasheet Summary
IS61VF51232 IS61VF51236 IS61VF10018
512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM
ISSI
®
ADVANCE INFORMATION October 2001
Features
- Internal self-timed write cycle
- Individual Byte Write Control and Global Write
- Clock controlled, registered address, data and control
- Linear burst sequence control using MODE input
- Three chip enable option for simple depth expansion and address pipelining
- mon data inputs and data outputs
- JEDEC 100-Pin TQFP and 119-pin PBGA package
- Single +2.5V, ±5% operation
- Auto Power-down during deselect
- Single cycle deselect
- Snooze MODE for reduced-power standby
- JTAG Boundary Scan for PBGA package
DESCRIPTION The ISSI...