Description
are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.
Features
- Internal self-timed write cycle.
- Individual Byte Write Control and Global Write.
- Clock controlled, registered address, data and control.
- Linear burst sequence control using MODE input.
- Three chip enable option for simple depth expansion and address pipelining.
- Common data inputs and data outputs.
- JEDEC 100-Pin TQFP and 119-pin PBGA package.
- Single +2.5V, ±5% operation.
- Auto Power-down during deselect.
- Sing.
IS61VF51232 Datasheet
