IS61VPD25636A - 256K x 36/ 512K x 18 9Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
ISSI (now Infineon)
Download the IS61VPD25636A datasheet PDF.
This datasheet also covers the IS61LPD25636A variant, as both devices belong to the same 256k x 36/ 512k x 18 9mb synchronous pipelined / double cycle deselect static ram family and are provided as variant models within a single manufacturer datasheet.
General Description
are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.
Key Features
Internal self-timed write cycle.
Individual Byte Write Control and Global Write.
Clock controlled, registered address, data and control.
Burst sequence control using MODE input.
Three chip enable option for simple depth expansion and address pipelining.
Note: The manufacturer provides a single datasheet file (IS61LPD25636A_IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for IS61VPD25636A (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
IS61VPD25636A. For precise diagrams, and layout, please refer to the original PDF.
IS61VPD25636A IS61LPD25636A IS61VPD51218A IS61LPD51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM www.DataSheet4U.com ISSI MAY 200...
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NED, DOUBLE CYCLE DESELECT STATIC RAM www.DataSheet4U.com ISSI MAY 2005 ® FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Double cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LPD: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VPD: VDD 2.5V + 5%, VDDQ 2.
IS61VPD25636A Datasheet
