DJLXT971A - Dual Speed Fast Ethernet PHY Transceiver
Intel
Download the DJLXT971A datasheet PDF.
This datasheet also covers the LXT-971 variant, as both devices belong to the same dual speed fast ethernet phy transceiver family and are provided as variant models within a single manufacturer datasheet.
General Description
at any time, without notice.
Key Features
3.3V Operation. Low power consumption (300 mW typical). Low-power “Sleep” mode. 10BASE-T and 100BASE-TX using a single RJ-45 connection. Supports auto-negotiation and parallel detection. MII interface with extended register capability. Robust baseline wander correction performance. 100BASE-FX fiber-optic capable. Standard CSMA/CD or full-duplex operation. Supports JTAG boundary scan.
Full PDF Text Transcription for DJLXT971A (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
DJLXT971A. For precise diagrams, and layout, please refer to the original PDF.
( DataSheet : www.DataSheet4U.com ) Intel® LXT971A 3.3V Dual-Speed Fast Ethernet PHY Transceiver Datasheet The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver ...
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asheet The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks. This document also supports the LXT971 device. The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition can be set using auto-negotiation, parallel detection, or manual control. The LXT971A is fabricated with an advanced CMOS process and requir
DJLXT971A Datasheet
