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Intel® Wireless Flash Memory (W18)
28F320W18, 28F640W18, 28F128W18
Datasheet
Product Features
■ High Performance Read-While-Write/ ■ Architecture
Erase
— Multiple 4-Mbit Partitions
— Burst frequency at 66 MHz
— Dual Operation: RWW or RWE
— 60 ns Initial Access Read Speed
— 8KB parameter blocks
— 11 ns Burst-Mode Read Speed
— 64KB main blocks
— 20 ns Page-Mode Read Speed
— Top or Bottom Parameter Devices
— 4-, 8-, 16-, and Continuous-Word Burst — 16-bit wide data bus
Mode Reads
— Burst and Page Mode Reads in all
Blocks, across all partition boundaries
— Burst Suspend Feature
— Enhanced Factory Programming at
3.1 µs/word (typ.for 0.13 µm)
■ Software
— 5 µs (typ.) Program and Erase Suspend
Latency Time
— Flash Data Integrator (FDI) and Common
Flash Interface (CFI) Compatible
— Programmable WAIT Signal Polarity
■ Security
■ Packaging and Power
— 128-bit Protection Register
— 0.13 µm: 32-, 64-, and 128-Mbit in VF
— 64-bits Unique Programmed by Intel
BGA Package; 128-Mbit in QUAD+
— 64-bits User-Programmable
Package
— Absolute Write Protection with VPP at
— 0.18 µm: 32- and 128-Mbit Densities in
Ground
VF BGA Package; 64-Mbit Density in
www.DataSheet4U.com—Individual and Instantaneous Block
Locking/Unlocking with Lock-Down
µBGA* Package
— 56 Active Ball Matrix, 0.75 mm Ball-
Capability
Pitch
■ Quality and Reliability
— Temperature Range: –40 °C to +85 °C
— 100k Erase Cycles per Block
— VCC = 1.70 V to 1.95 V
— VCCQ = 1.70 V to 2.24 V or 1.35 V to
1.80 V
— 0.13 µm ETOX™ VIII Process
— 0.18 µm ETOX™ VII Process
— Standby current (0.13 µm): 8µA (typ.)
— Read current: 7mA (typ.)
The Intel® Wireless Flash Memory (W18) device with flexible multi-partition dual operation,
provides high-performance asynchronous and synchronous burst reads. It is an ideal memory for
low-voltage burst CPUs. Combining high read performance with flash memory’s intrinsic non-
volatility, the W18 device eliminates the traditional system-performance paradigm of shadowing
redundant code memory from slow nonvolatile storage to faster execution memory. It reduces
the total memory requirement that increases reliability and reduces overall system power
consumption and cost.
The W18 device’s flexible multi-partition architecture allows programming or erasing to occur
in one partition while reading from another partition. This allows for higher data write
throughput compared to single partition architectures. The dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take
place in the background. The designer can also choose the size of the code and data partitions via
the flexible multi-partition architecture.
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Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
290701-009
December 2003
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