Datasheet4U Logo Datasheet4U.com

RD38F4455LVY - (RD38F4455LVY / RD38F4050L0Z) Wireless Memory System

Download the RD38F4455LVY datasheet PDF. This datasheet also covers the RD38F4050L0Z variant, as both devices belong to the same (rd38f4455lvy / rd38f4050l0z) wireless memory system family and are provided as variant models within a single manufacturer datasheet.

Description

at any time, without notice.

Features

  • Device Architecture.
  • xRAM Performance.
  • Code and data segment: 128- and 256.
  • PSRAM at 1.8 V I/O : 85 ns initial Mbit density; PSRAM: 32- and 64-Mbit access, 30 ns async page reads; 65 ns density; SRAM: 8 Mbit density. initial access, 18 ns async page.
  • Top or bottom parameter configuration.
  • SRAM at 1.8 or 3.0 V I/O: 70 ns initial access.
  • Asymmetrical blocking structure.
  • Flash Performance.
  • 16-KWord.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (RD38F4050L0Z_Intel.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number RD38F4455LVY
Manufacturer Intel
File Size 1.38 MB
Description (RD38F4455LVY / RD38F4050L0Z) Wireless Memory System
Datasheet download datasheet RD38F4455LVY Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
RD38F1010C0ZTL0 (RD38Fxxxx) Flash Memory Intel Corporation
RD38F1010xxxx (RD38Fxxxx) Flash Memory Intel Corporation
RD38Fxxxxxx (RD38Fxxxx) Flash Memory Intel Corporation
RD3.0E Zener diode Excel Semiconductor
RD3.0E SILICON ZENER DIODES EIC

Other Datasheets by Intel

Part Number Description
RD38F4460LVY Wireless Memory System
RD38F4050L0Z (RD38F4455LVY / RD38F4050L0Z) Wireless Memory System
RD38F2010 (RD38F2xxx) FLASH+PSRAM
RD38F2020 (RD38F2xxx) FLASH+PSRAM
RD38F2030 (RD38F2xxx) FLASH+PSRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com Intel StrataFlash£ Wireless Memory System (LV18/LV30 SCSP) 768-Mbit LVQ Family with Asynchronous Static RAM Datasheet Product Features ■ ■ ■ ■ ■ Device Architecture ■ xRAM Performance — Code and data segment: 128- and 256— PSRAM at 1.8 V I/O : 85 ns initial Mbit density; PSRAM: 32- and 64-Mbit access, 30 ns async page reads; 65 ns density; SRAM: 8 Mbit density. initial access, 18 ns async page. — Top or bottom parameter configuration. — SRAM at 1.8 or 3.0 V I/O: 70 ns initial access. — Asymmetrical blocking structure. ■ Flash Performance — 16-KWord parameter blocks (Top or — Code Segment at 1.8 V I/O: 85 ns initial Bottom); 64-K Word main blocks. access; 25 ns async page read; 14 ns — Zero-latency block locking. sync reads (tCHQV); 54 MHz CLK.
Published: |