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Intersil Electronic Components Datasheet

29103BRA Datasheet

16K x 1 Asynchronous CMOS Static RAM

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HM-65262
March 1997
16K x 1 Asynchronous
CMOS Static RAM
Features
• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout
• No Clocks or Strobes Required
• Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required
Ordering Information
Description
The HM-65262 is a CMOS 16384 x 1-bit Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle times and ease of use. The HM-65262
is available in both JEDEC standard 20 pin, 0.300 inch wide
CERDIP and 20 pad CLCC packages, providing high board-
level packing density. Gated inputs lower standby current,
and also eliminate the need for pull-up or pull-down resis-
tors.
The HM-65262, a full CMOS RAM, utilizes an array of six
transistor (6T) memory cells for the most stable and lowest
possible standby supply current over the full military temper-
ature range. In addition to this, the high stability of the 6T
RAM cell provides excellent protection against soft errors
due to noise and alpha particles. This stability also improves
the radiation tolerance of the RAM over that of four transistor
(4T) devices.
PACKAGE
CERDIP
JAN #
SMD#
CLCC (SMD#)
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
70ns/20µA (NOTE 1) 85ns/20µA (NOTE 1)
HM1-65262B-9
HM1-65262-9
29109BRA
29103BRA
8413203RA
8413201RA
8413203YA
8413201YA
(NOTE 1)
85ns/400µA
-
-
-
-
PKG. NO.
F20.3
F20.3
F20.3
J20.C
NOTE:
1. Access Time/Data Retention Supply Current.
Pinouts
HM-65262 (CERDIP)
TOP VIEW
HM-65262 (CLCC)
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
Q8
W9
GND 10
20 VCC
19 A13
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
12 D
11 E
A2 3
A3 4
A4 5
A5 6
A6 7
Q8
2 1 20 19
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
9 10 11 12
A0 - A13
Address Input
E Chip Enable/Power Down
Q Data Out
D Data In
VSS/GND Ground
VCC Power (+5)
W Write Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 3002.2


Intersil Electronic Components Datasheet

29103BRA Datasheet

16K x 1 Asynchronous CMOS Static RAM

No Preview Available !

Functional Diagram
A0
A1
A2
A3
A4
A12
A13
D
E
W
HM-65262
ROW
ADDRESS
BUFFER
A
7 ROW
A
DECODER
(1 OF 128)
128
7
MEMORY ARRAY
128 X 128
128
COLUMN DECODER
(1 OF 128)
AND I / O CIRCUITRY
AA
77
COLUMN
ADDRESS BUFFERS
Q
6-2


Part Number 29103BRA
Description 16K x 1 Asynchronous CMOS Static RAM
Maker Intersil
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29103BRA Datasheet PDF






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