Datasheet4U Logo Datasheet4U.com

ACTS08MS - Radiation Hardened Quad 2-Input AND Gate

Description

The Intersil ACTS08MS is a radiation hardened quad 2-Input AND Gate.

A high on both inputs forces the output to a high logic level.

The ACTS08MS utilizes advanced CMOS/SOS technology to achieve high-speed operation.

Features

  • 1.25 Micron Radiation Hardened SOS CMOS.
  • Total Dose 300K RAD (Si).
  • Single Event Upset (SEU) Immunity 80 MEV-cm /mg.
  • Dose Rate Upset >10 11 2 RAD (Si)/s, 20ns Pulse.
  • Latch-Up Free Under Any Conditions.
  • Military Temperature Range: -55oC to +125oC.
  • Significant Power Reduction Compared to ALSTTL Logic.
  • DC Operating Voltage Range: 4.5V to 5.5V.
  • Input Logic Le.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ACTS74MS Radiation Hardened Dual-D Flip-Flop Intersil
ACT-D1M96S ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module Aeroflex Circuit Technology
ACT-E128K32 High Speed 4 Megabit EEPROM Multichip Module Aeroflex
ACT-F128K32 High Speed 4 Megabit FLASH Multichip Module Aeroflex
ACT-F128K8 High Speed 1 Megabit Monolithic FLASH Aeroflex

Other Datasheets by Intersil (Renesas)

Part Number Description
ACTS00MS Radiation Hardened Quad 2-Input NAND Gate
ACTS10MS Radiation Hardened Triple Three-Input NAND Gate
ACTS112MS Radiation Hardened Dual J-K Flip-Flop
ACTS125MS Radiation Hardened Quad Buffer/ Three-State
ACTS138MS Radiation Hardened TTL Input/ 3-to-8 Line Decoder/Demultiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ACTS08MS April 1995 Radiation Hardened Quad 2-Input AND Gate Pinouts 14 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C TOP VIEW A1 1 B1 2 Y1 3 A2 4 B2 5 Y2 6 GND 7 14 VCC 13 B4 12 A4 11 Y4 10 B3 9 A3 8 Y3 Features • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose 300K RAD (Si) • Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ) • SEU LET Threshold >80 MEV-cm /mg • Dose Rate Upset >10 11 2 RAD (Si)/s, 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels - VIL = 0.
Published: |