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Intersil Electronic Components Datasheet

CD4041UBMS Datasheet

CMOS Quad True/Complement Buffer

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Data Sheet
CD4041UBMS
December 1992
File Number 3309
CMOS Quad True/Complement Buffer
CD4041UBMS types are quad true/complement buffers con-
sisting of n- and p- channel units having low channel resis-
tance and high current (sourcing and sinking) capability. The
CD4041UBMS is intended for use as a buffer, line driver, or
CMOS-to-TTL driver. It can be used as an ultra-low power
resistor-network driver for A/D and D/A conversion, as a
transmission-line driver, and in other applications where high
noise immunity and low power dissipation are primary
design requirements.
The CD4041UBMS is supplied in these 14 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
Pinout
CD4041UBMS
TOP VIEW
E=A 1
F=A 2
A3
G=B 4
H=B 5
B6
VSS 7
14 VDD
13 D
12 N = D
11 M = D
10 C
9 L=C
8 K=C
Features
• High Voltage Type (20V Rating)
• Balanced Sink and Source Current; Approximately 4
Times Standard “B” Drive
• Equalized Delay to True and Complement Outputs
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specificationsfor Description of
‘B’ Series CMOS Devices”
Applications
• High Current Source/Sink Driver
• CMOS-to-DTL/TTL Converter Buffer
• Display Driver
• MOS Clock Driver
• Resistor Network Driver (Ladder or Weighted R)
• Buffer
• Transmission Line Driver
Functional Diagram
3
A
6
B
10
C
13
D
VSS = 7
VDD = 14
1
E
E=A
2
F
F=A
4
G
G=B
5
H
H=B
8
K
K=C
9
L
L=C
11
M
M=D
12
N
N=D
VDD
VDD VDD
INPUT*
TRUE
OUTPUT
VSS
*ALL INPUTS PROTECTED
BY CMOS INPUT
PROTECTION NETWORK
VSS
VSS
P
N
VSS
VDD
COMPLEMENT
OUTPUT
VDD
VSS
FIGURE 1. SCHEMATIC DIAGRAM 1 OF 4 BUFFERS
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999


Intersil Electronic Components Datasheet

CD4041UBMS Datasheet

CMOS Quad True/Complement Buffer

No Preview Available !

CD4041UBMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance. . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . .
80oθCja/W
20oθCjc/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
Input Leakage Current
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
SYMBOL
CONDITIONS (NOTE 1)
IDD VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
IIL VIN = VDD or GND VDD = 20
VDD = 18V
IIH VIN = VDD or GND VDD = 20
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VIL
VDD = 18V
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
MIN MAX UNITS
1
+25oC
- 2 µA
2
+125oC
- 200 µA
3
-55oC
- 2 µA
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
3
-55oC
-100
-
nA
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
3
-55oC
- 100 nA
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
1
+25oC
1.6 - mA
1
+25oC
5.0 - mA
1
+25oC
19 - mA
1
+25oC
- -1.6 mA
1
+25oC
- -6.4 mA
1
+25oC
- -5.0 mA
1
+25oC
- -19 mA
1
+25oC
-2.8 -0.7
V
1
+25oC
0.7 2.8
V
7
+25oC
VOH > VOL < V
7
+25oC
VDD/2 VDD/2
8A +125oC
8B -55oC
1, 2, 3
+25oC, +125oC, -55oC -
1.0 V
1, 2, 3
+25oC, +125oC, -55oC 4.0
-
V
1, 2, 3
+25oC, +125oC, -55oC -
2.5 V
1, 2, 3
+25oC, +125oC, -55oC 12.5
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being im- 3. For accuracy, voltage is measured differentially to VDD. Limit is
plemented.
0.050V max.
2. Go/No Go test with limits applied to inputs.
2


Part Number CD4041UBMS
Description CMOS Quad True/Complement Buffer
Maker Intersil Corporation
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CD4041UBMS Datasheet PDF






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