HCS20MS Datasheet | Intersil

Features - 3 Micron Radiation Hardened SOS CMOS - Total Dose 200K RAD (Si) - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) - Dose Rate Survivability: >1 x 1012 RAD (Si)/s - Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse - Latch-Up Free Under Any Conditions - Military Temperature Range: -55o C to +125o C - Significant Power Reduction pared to LSTTL ICs - DC Operating Voltage Range: 4.5V to 5.5V - Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min - Input Current Levels Ii ≤ 5µA at VOL, VOH 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-183S CDFP3-F14, LEAD FINISH C TOP VIEW A1 B1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D2 C2 NC B2 A2 Y2 Description The Intersil HCS20MS is a Radiation Hardened Dual 4-Input NAND Gate. A low on any input forces the output to a High state. The HCS20MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS20MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). NC C1 D1 Y1 GND Functional Diagram (1, 9) An Bn (2, 10) Ordering Information PART NUMBER HCS20DMSR TEMPERATURE RANGE -55o C to +125o C SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample PACKAGE 14 Lead SBDIP (6, 8) Yn (4, 12) Cn Dn (5, 13) HCS20KMSR -55o C to +125o C 14 Lead Ceramic Flatpack 14 Lead SBDIP An L TRUTH TABLE INPUTS Bn X L X X H Cn X X L X H Dn X X X L H OUTPUTS Yn H H H H L HCS20D/ Sample HCS20K/ Sample HCS20HMSR +25o C +25o C Sample 14 Lead Ceramic Flatpack Die +25o C Die NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 Spec Number File...