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HM-6561883 - 256 x 4 CMOS RAM

General Description

The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology.

Synchronous circuit design techniques are employed to achieve high performance and low power operation.

Key Features

  • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
  • Low Power Standby.
  • 50µW Max.
  • Low Power Operation.
  • . . . 20mW/MHz Max.
  • Fast Access Time.
  • . . 200ns Max.
  • Data Retention.
  • . . . . at 2.0V Min.
  • TTL Compatible Input/Output.
  • High Output Drive - 1 TTL L.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HM-6561/883 March 1997 256 x 4 CMOS RAM Description The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On-chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The data inputs and outputs are multiplexed internally for common I/O bus compatibility. The HM-6561/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.