HM-6561883 Datasheet | Intersil

Description The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On-chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The data inputs and outputs are multiplexed internally for mon I/O bus patibility. The HM-6561/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features - This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. - Low Power Standby - - - - 50µW Max - Low Power Operation - - . . . 20m W/MHz Max - Fast Access Time- - - - . . 200ns Max - Data Retention - - - - . . . .at 2.0V Min - TTL patible Input/Output - High Output Drive - 1 TTL Load - On-Chip Address Registers - mon Data In/Out - Three-State Output - Easy Microprocessor Interfacing Ordering Information PACKAGE TEMPERATURE RANGE CERDIP -55o C to +125o C 220ns HM1-6561B/883 300ns HM1-6561/883 PKG. NO. F18.3 Pinout HM-6561/883 (CERDIP) TOP VIEW A3 A2 A1 A0 A5 A6 A7 GND E 1 2 3 4 5 6 7 8 9 18 VCC 17 A4 16 W 15 S1 14 DQ3 13 DQ2 12 DQ1 11 DQ0 10 S2 PIN A E W S DQ DESCRIPTION Address Input Chip Enable Write Enable Chip Select Data In/Out CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://.intersil. or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 6-117 HM-6561/883 Functional Diagram A0 A1 A5 A6 A7 A LATCHED ADDRESS REGISTER 5 A 5 L G A D DQ0 A Q LATCH L D DQ1 A Q LATCH L D DQ2 A Q LATCH L D DQ3 A Q LATCH L A L...