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Intersil Electronic Components Datasheet

HM-6642 Datasheet

512 x 8 CMOS PROM

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HM-6642
March 1997
512 x 8 CMOS PROM
Features
Description
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 120/200ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• Field Programmable
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
The HM-6642 is a 512 x 8 CMOS NiCr fusible link
Programmable Read Only Memory in the popular 24 pin,
byte wide pinout. Synchronous circuit design techniques
combine with CMOS processing to give this device high
speed performance with very low power dissipation.
On-chip address latches are provided, allowing easy
interfacing with recent generation microprocessors that use
multiplexed address/data bus structures, such as the 8085.
The output enable controls, both active low and active high,
further simplify microprocessor system interfacing by
allowing output data bus control independent of the chip
enable control. The data output latches allow the use of the
HM-6642 in high speed pipelined architecture systems, and
also in synchronous logic replacement functions.
Applications for the HM-6642 CMOS PROM include low
power handheld microprocessor based instrumentation and
communications systems, remote data acquisition and
processing systems, processor control store, and synchro-
nous logic replacement.
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
Ordering Information
PACKAGE
SBDIP
SMD#
SLIM SBDIP
SMD#
CLCC
SMD#
TEMPERATURE RANGE
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
120ns
HM1-6642B-9
5962-8869002JA
HM6-6642B-9
5962-8869002LA
-
5962-88690023A
200ns
HM1-6642-9
5962-8869001JA
HM6-6642-9
5962-8869001LA
HM4-6642-9
5962-88690013A
PKG. NO.
D24.6
D24.6
D24.3
D24.3
J28.A
J28.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 3012.1


Intersil Electronic Components Datasheet

HM-6642 Datasheet

512 x 8 CMOS PROM

No Preview Available !

HM-6642
Pinouts
HM-6642 (SBDIP)
TOP VIEW
HM-6642 (CLCC)
TOP VIEW
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
Q0 9
Q1
10
Q2
11
GND
12
24 VCC
23 A8
22 G1
21 G2
20 G3
19 E
18 P
17 Q7
16 Q6
15 Q5
14 Q4
13 Q3
4 3 2 1 28 27 26
A4 5
25 G2
A3 6
24 G3
A2 7
23 E
A1 8
22 P
A0 9
21 NC
NC 10
20 Q7
Q0 11
19 Q6
12 13 14 15 16 17 18
PIN DESCRIPTION
PIN DESCRIPTION
NC No Connect
A0-A8
Address Inputs
E Chip Enable
Q Data Output
VCC
Power (+5V)
G1, G2, G3 Output Enable
P (Note) Program Enable
NOTE: P should be hardwired to GND
except during programming.
Functional Diagram
A8 A
A7
A6
LATCHED
6 GATED
ADDRESS
ROW
A5
A4
REGISTER
A
DECODER
64
A3 6
64 x 64
MATRIX
ALL LINES POSITIVE LOGIC - ACTIVE HIGH
THREE STATE BUFFERS:
A HIGH
OUTPUT ACTIVE
A
A2
A1
A0
LATCHED
ADDRESS
REGISTER
3
A
3
88 8888 8 8
GATED COLUMN
DECODER
D
DATA LATCHES:
L HIGH
Q=D
Q LATCHES ON RISING EDGE OF E
ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF E
P SHOULD BE HARDWIRED TO GND EXCEPT
DURING PROGRAMMING
E 8-BIT DATA LATCH
G1
G2
G3
Q0 Q1 Q2 Q3
Q4 Q5 Q6 Q7
6-2


Part Number HM-6642
Description 512 x 8 CMOS PROM
Maker Intersil Corporation
Total Page 8 Pages
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