HSP48212
Overview
- 12-Bit Pixel Data
- Two’s Complement or Unsigned Data
- 12-Bit Mix Factor
- 13-Bit Signed or Unsigned Three State Output
- Overflow Detection and Output Saturation
- Rounding to 8, 10, 12, or 13-Bits
- Input and Output Pixel Data Synchronous to Clock
- Programmable Pipeline Delay of up to 7 Clock Cycles for Control of Misaligned Input Data
- TTL Compatible Inputs/Outputs
- DC to 40MHz Clock Rate
