HSP43168 Datasheet - Intersil Corporation

HSP43168 Dual FIR Filter

SYMBOL VCC GND CIN0-9 A0-8 I I TYPE VCC: +5V power supply pin. Ground. Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB. Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the LSB. C.

HSP43168 Data Sheet November 1999 File Number 2808.8 Dual FIR Filter The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR ﬁlters. Each ﬁlter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefﬁcients. The Block Diagram shows two FIR cells each fed by a separate coefﬁcient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be conﬁgured to provide q.

HSP43168 Features

* Two Independent 8-Tap FIR Filters Conﬁgurable as a Single 16-Tap FIR

* 10-Bit Data and Coefﬁcients

* On-Board Storage for 32 Programmable Coefficient Sets

* Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 19-Bit Data and Coefﬁcients

* Programmable Decimati

HSP43168 Datasheet (325.84 KB)