HSP48901 Datasheet | Intersil

Features - DC to 30MHz Clock Rate - Configurable for 1-D and 2-D Correlation/Convolution - Dual Coefficient Mask Registers, Switchable in a Single Clock Cycle - Two’s plement or Unsigned 8-Bit Input Data and Coefficients - 20-Bit Extended Precision Output - Standard µP Interface Applications - Image Filtering - Edge Detection/Enhancement - Pattern Matching - Real Time Video Filters Ordering Information PART NUMBER HSP48901JC-20 HSP48901JC-30 HSP48901GC-20 HSP48901GC-30 TEMP. RANGE (o C) 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 68 Ld PLCC 68 Ld PLCC 68 Ld PGA 68 Ld PGA PKG. NO. N68.95 N68.95 G68.A G68.A Block Diagram DIN3 (0-7) DIN2 (0-7) DIN1 (0-7) Z -1 Z -1 Z -1 MODE CIN0-7 FRAME Z -1 Z -1 A0-2 LD 3 ADDRESS DECODER INTERNAL CLOCK CLK HOLD CLOCK GEN I H G Z -1 F E D 2:1 Z -1 Z -1 Z -1 C B A MODE 2:1 Z -1 Z -1 Z -1 CONTROL LOGIC Z -1 Z -1 + Z -1 Z -1 Z -1 + Z -1 + Z -1 Z -1 Z -1 Z -1 + Z -1 DOUT 0-19 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://.intersil. or 407-727-9207 | Copyright © Intersil Corporation 1999 HSP48901 Pinouts 68 LEAD PLCC TOP VIEW VCC DIN1 (0) DIN1 (1) DIN1 (2) DIN1 (3) DIN1 (4) DIN1 (5) DIN1 (6) DIN1 (7) GND DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 VCC 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 DIN2 (7) DIN2 (6) DIN2 (5) DIN2 (4) DIN2 (3) DIN2 (2) DIN2 (1) DIN2 (0) GND DIN3 (7) DIN3 (6) DIN3 (5) DIN3 (4) DIN3 (3) DIN3 2) DIN3 (1) DIN3 (0) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC CLK GND CIN7 CIN6 CIN5 CIN4 CIN3 CIN2 CIN1 CIN0 GND LD HOLD A2 A1 A0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 DOUT6 DOUT7 DOUT8 DOUT9 GND DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15 DOUT16 DOUT17 DOUT18 DOUT19 VCC...