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ISPPAC-CLK56xxA - In-System Programmable

Description

The ispClock5610A and ispClock5620A are in-system-programmable high-fanout enhanced zero delay clock generators designed for use in high performance communications and computing applications.

Features

  • 8MHz to 400MHz Input/Output Operation Low Output to Output Skew (.

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Datasheet Details

Part number ISPPAC-CLK56xxA
Manufacturer Lattice Semiconductor
File Size 1.39 MB
Description In-System Programmable
Datasheet download datasheet ISPPAC-CLK56xxA Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com ispClock 5600A Family ™ In-System Programmable, Enhanced Zero-Delay Clock Generator with Universal Fan-Out Buffer December 2005 Preliminary Data Sheet Features ■ ■ ■ ■ 8MHz to 400MHz Input/Output Operation Low Output to Output Skew (<50ps) Low Jitter Peak-to-Peak Up to 20 Programmable Fan-out Buffers • Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, eHSTL, SSTL, LVDS, LVPECL, Differential HSTL, SSTL • Programmable output impedance - 40 to 70Ω in 5Ω increments • Programmable slew rate • Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.
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