The ispClock5610 and ispClock5620 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications.
Key Features
10MHz to 320MHz Input/Output Operation Low Output to Output Skew (.
Full PDF Text Transcription for ISPPAC-CLK56xx (Reference)
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ISPPAC-CLK56xx. For precise diagrams, and layout, please refer to the original PDF.
ispClock 5600 Family ™ In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer November 2004 Preliminary Data Sheet Features ■ ■ ■ ■ 10MHz to 320...
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fer November 2004 Preliminary Data Sheet Features ■ ■ ■ ■ 10MHz to 320MHz Input/Output Operation Low Output to Output Skew (<50ps) Low Jitter Peak-to-Peak (<60ps) Up to 20 Programmable Fan-out Buffers • Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, SSTL, LVDS, LVPECL • Programmable output impedance - 40 to 70Ω in 5Ω increments • Programmable slew rate • Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.
ISPPAC-CLK56xx Datasheet
