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ISPXPLD5000MX - eXpanded Programmable Logic Device XPLD

Key Features

  • Flexible Multi-Function Block (MFB) Architecture.
  • SuperWIDE™ logic (up to 136 inputs).
  • Arithmetic capability.
  • Single- or Dual-port SRAM.
  • FIFO.
  • Ternary CAM.
  • sysCLOCK™ PLL Timing Control.
  • Multiply and divide between 1 and 32.
  • Clock shifting capability.
  • External feedback capability.
  • sysIO™ Interfaces.
  • LVCMOS 1.8, 2.5, 3.3V.
  • Programmable impedance.
  • Hot-socketing.
  • Flexible bus-m.

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Datasheet Details

Part number ISPXPLD5000MX
Manufacturer Lattice Semiconductor
File Size 860.30 KB
Description eXpanded Programmable Logic Device XPLD
Datasheet download datasheet ISPXPLD5000MX Datasheet

Full PDF Text Transcription for ISPXPLD5000MX (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for ISPXPLD5000MX. For precise diagrams, and layout, please refer to the original PDF.

DISSECLOENCTTINDUEEVIDCES ispXPLDTM 5000MX Family 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family February 2010 Data Sheet Feat...

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d Programmable Logic Device XPLD™ Family February 2010 Data Sheet Features  Flexible Multi-Function Block (MFB) Architecture • SuperWIDE™ logic (up to 136 inputs) • Arithmetic capability • Single- or Dual-port SRAM • FIFO • Ternary CAM  sysCLOCK™ PLL Timing Control • Multiply and divide between 1 and 32 • Clock shifting capability • External feedback capability  sysIO™ Interfaces • LVCMOS 1.8, 2.5, 3.3V – Programmable impedance – Hot-socketing – Flexible bus-maintenance (Pull-up, pulldown, bus-keeper, or none) – Open drain operation • SSTL 2, 3 (I & II) • HSTL (I, III, IV) • PCI 3.3 • GTL+ • LVDS • LVPECL • LVTTL Table

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