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MACRONIX

MX25V512F Datasheet Preview

MX25V512F Datasheet

CMOS MXSMIO FLASH MEMORY

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MX25V512F
MX25V512F
2.3V-3.6V, 512K-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
2.3V-3.6V for Read, Erase and Program Operations
• Unique ID and Secure OTP Support
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Program Suspend/Resume & Erase Suspend/Resume
P/N: PM2314
Rev. 1.2, April 18, 2017
1




MACRONIX

MX25V512F Datasheet Preview

MX25V512F Datasheet

CMOS MXSMIO FLASH MEMORY

No Preview Available !

MX25V512F
Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 5
Table 1. Additional Feature...........................................................................................................................6
3. PIN CONFIGURATIONS .......................................................................................................................................... 7
4. PIN DESCRIPTION................................................................................................................................................... 7
5. BLOCK DIAGRAM.................................................................................................................................................... 8
6. DATA PROTECTION................................................................................................................................................. 9
Table 2. Protected Area Sizes....................................................................................................................10
Table 3. 8K-bit Secured OTP Definition..................................................................................................... 11
7. MEMORY ORGANIZATION.................................................................................................................................... 12
Table 4. Memory Organization...................................................................................................................12
8. DEVICE OPERATION............................................................................................................................................. 13
9. HOLD FEATURE..................................................................................................................................................... 15
10. COMMAND DESCRIPTION.................................................................................................................................. 16
Table 5. Command Set...............................................................................................................................16
10-1. Write Enable (WREN)............................................................................................................................... 19
10-2. Write Disable (WRDI)................................................................................................................................ 20
10-3. Read Identification (RDID)........................................................................................................................ 21
10-4. Read Electronic Signature (RES)............................................................................................................. 22
10-5. Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 23
10-6. ID Read..................................................................................................................................................... 24
Table 6. ID Definitions ...............................................................................................................................24
10-7. Read Status Register (RDSR).................................................................................................................. 25
Table 7. Status Register.............................................................................................................................28
Table 8. Configuration Register..................................................................................................................29
Table 9. Dummy Cycle Table......................................................................................................................29
10-8. Read Configuration Register (RDCR)....................................................................................................... 30
10-9. Write Status Register (WRSR).................................................................................................................. 31
Table 10. Protection Modes........................................................................................................................32
10-10. Read Data Bytes (READ)......................................................................................................................... 35
10-11. Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 36
10-12. Dual Read Mode (DREAD)....................................................................................................................... 37
10-13. 2 x I/O Read Mode (2READ).................................................................................................................... 38
10-14. Quad Read Mode (QREAD)..................................................................................................................... 39
10-15. 4 x I/O Read Mode (4READ).................................................................................................................... 40
10-16. Burst Read................................................................................................................................................ 42
10-17. Performance Enhance Mode.................................................................................................................... 43
10-18. Sector Erase (SE)..................................................................................................................................... 45
10-19. Block Erase (BE32K)................................................................................................................................ 46
10-20. Block Erase (BE)...................................................................................................................................... 47
10-21. Chip Erase (CE)........................................................................................................................................ 48
10-22. Page Program (PP).................................................................................................................................. 49
P/N: PM2314
Rev. 1.2, April 18, 2017
2


Part Number MX25V512F
Description CMOS MXSMIO FLASH MEMORY
Maker MACRONIX
Total Page 30 Pages
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