P2S28D30CTP dram equivalent, (p2s28d30ctp / p2s28d40ctp) 128m double data rate synchronous dram.
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differe.
P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals www.DataSheet4U.com are referenced to the rising edge of CLK. .
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