P2S28D40CTP Datasheet | MIRA

DESCRIPTION P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals .. are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK. The P2S28D30/40CTP achieves very high speed clock rate up to 200 MHz . FEATURES - Vdd=Vddq=2.5V+0.2V - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - mands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency - 2.0 / 2.5/ 3 (programmable) ; Burst length - 2 / 4 / 8 (programmable) Burst type - Sequential / Interleave (programmable) - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles / 64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-11 / Column address A0-9 , A0-9(x8) /A0-8(x16) - SSTL_2 Interface - Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch - JEDEC standard for -6 , -75 - Intel standard for -5 DDR SDRAM (Rev.1.0) Deutron Electronics Corp. PDF created with pdf Factory Pro trial version .pdffactory. Deutron Electronics Corp. P2S28D30/40CTP 128M Double Data Rate Synchronous DRAM Pin Assignment (Top View) 66-pin TSOP .. /CLK,CLK CKE /CS /RAS /CAS /WE DQ0-15 UDM, LDM : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Write Mask (x16) A0-11 BA0,1 Vdd Vdd Q Vss Vss Q : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output DDR SDRAM (Rev.1.0) Deutron Electronics Corp. PDF...