P2S28D40CTP Datasheet (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM

Manufacturer: MIRA

Overview: Deutron Electronics Corp. P2S28D30/40CTP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice.

Download the P2S28D40CTP datasheet PDF. This datasheet also includes the P2S28D30CTP variant, as both parts are published together in a single manufacturer document.

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P2S28D40CTP (p2s28d30ctp / p2s28d40ctp) 128m double data rate synchronous dram by MIRA - Datasheet Preview

Datasheet Details

Part number	P2S28D40CTP
Manufacturer	MIRA
File Size	301.58 KB
Description	(P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM
Download	P2S28D40CTP Download (PDF)

General Description

P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals www.DataSheet4U.com are referenced to the rising edge of CLK.

Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK.

Key Features

- Vdd=Vddq=2.5V+0.2V - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency.
2.0 / 2.5/ 3 (programmable) ; Burst length -.

More Datasheets from MIRA

Part Number	Description
P2S28D30CTP	(P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM