DS32506/DS32508/DS32512
TABLE OF CONTENTS
1. STANDARDS COMPLIANCE .............................................................................................6
2. BLOCK DIAGRAM ..............................................................................................................7
3. APPLICATION EXAMPLE ..................................................................................................8
4. DETAILED DESCRIPTION..................................................................................................9
5. DETAILED FEATURES.....................................................................................................11
5.1 GLOBAL FEATURES .......................................................................................................................11
5.2 RECEIVER .....................................................................................................................................11
5.3 TRANSMITTER ...............................................................................................................................11
5.4 JITTER ATTENUATOR .....................................................................................................................11
www.D5a.t5aSheBetI4TUE.cRoRmOR-RATE TESTER (BERT) FEATURES ...............................................................................12
5.6 CLOCK ADAPTER...........................................................................................................................12
5.7 PARALLEL MICROPROCESSOR INTERFACE FEATURES.....................................................................12
5.8 SPI SERIAL MICROPROCESSOR INTERFACE FEATURES ..................................................................12
5.9 MISCELLANEOUS FEATURES ..........................................................................................................12
5.10 TEST FEATURES............................................................................................................................12
5.11 LOOPBACK FEATURES ...................................................................................................................12
6. CONTROL INTERFACE MODES......................................................................................13
7. PIN DESCRIPTIONS .........................................................................................................14
7.1 SHORT PIN DESCRIPTIONS ............................................................................................................14
7.2 DETAILED PIN DESCRIPTIONS ........................................................................................................17
8. FUNCTIONAL DESCRIPTION ..........................................................................................24
8.1 LIU MODE ....................................................................................................................................24
8.2 TRANSMITTER ...............................................................................................................................24
8.2.1 Transmit Clock .................................................................................................................................... 24
8.2.2 Framer Interface Format and the B3ZS/HDB3 Encoder..................................................................... 24
8.2.3 Error Insertion ..................................................................................................................................... 24
8.2.4 AIS Generation.................................................................................................................................... 25
8.2.5 Waveshaping ...................................................................................................................................... 25
8.2.6 Line Build-Out ..................................................................................................................................... 25
8.2.7 Line Driver........................................................................................................................................... 25
8.2.8 Interfacing to the Line ......................................................................................................................... 25
8.2.9 Driver Monitor and Output Failure Detection ...................................................................................... 26
8.2.10 Power-Down........................................................................................................................................ 26
8.2.11 Jitter Generation (Intrinsic).................................................................................................................. 26
8.2.12 Jitter Transfer ...................................................................................................................................... 26
8.3 RECEIVER .....................................................................................................................................30
8.3.1 Interfacing to the Line ......................................................................................................................... 30
8.3.2 Optional Preamp ................................................................................................................................. 30
8.3.3 Automatic Gain Control (AGC) and Adaptive Equalizer ..................................................................... 30
8.3.4 Clock and Data Recovery (CDR) ........................................................................................................ 31
8.3.5 Loss-of-Signal (LOS) Detector............................................................................................................ 31
8.3.6 Framer Interface Format and the B3ZS/HDB3 Decoder .................................................................... 32
8.3.7 Power-Down........................................................................................................................................ 33
8.3.8 Input Failure Detection........................................................................................................................ 33
8.3.9 Jitter and Wander Tolerance............................................................................................................... 34
8.3.10 Jitter Transfer ...................................................................................................................................... 35
8.4 JITTER ATTENUATOR .....................................................................................................................35
8.5 BERT...........................................................................................................................................36
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