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DS34S104 - (DS34S101 - DS34S108) Single/Dual/Quad/Octal TDM-over-Packet Chip

Download the DS34S104 datasheet PDF. This datasheet also covers the DS34S101 variant, as both devices belong to the same (ds34s101 - ds34s108) single/dual/quad/octal tdm-over-packet chip family and are provided as variant models within a single manufacturer datasheet.

Description

These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks.

Features

  • es Transport of E1, T1, E3, T3 or STS-1 TDM or CBR Serial Signals Over Packet Networks Full Support for These Mapping Methods: SAToP, CESoPSN, TDMoIP (AAL1), HDLC, Unstructured, Structured, Structured with CAS Adaptive Clock Recovery, Common Clock, External Clock and Loopback Timing Modes On-Chip TDM Clock Recovery Machines, One Per Port, Independently Configurable Clock Recovery Algorithm Handles Network PDV, Packet Loss, Constant Delay Changes, Frequency Changes and Other Impairments 64 Indepe.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS34S101_MaximIntegratedProducts.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Maxim Integrated (Analog Devices)

Part Number Description
DS34S101 (DS34S101 - DS34S108) Single/Dual/Quad/Octal TDM-over-Packet Chip
DS34S102 (DS34S101 - DS34S108) Single/Dual/Quad/Octal TDM-over-Packet Chip
DS34S108 (DS34S101 - DS34S108) Single/Dual/Quad/Octal TDM-over-Packet Chip
DS34S132 32-Port TDM-over-Packet IC
DS34T101 (DS34T101 - DS34T108) Single/Dual/Quad/Octal TDM-Over-Packet Chip

Full PDF Text Transcription

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ABRIDGED DATA SHEET www.DataSheet4U.com Rev: 101708 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles. All standardsbased TDM-over-packet mapping methods are supported except AAL2. Frame-based serial HDLC data flows are also supported. The high level of integration available with the DS34S10x devices minimizes cost, board space, and time to market.
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